TechNiPr0

--generic parity detector:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity genericparitydetector is
generic(n:integer:=8);
port(a:in std_logic_vector(n downto 0);
y:out std_logic_vector(n+1 downto 0));
end genericparitydetector;

architecture Behavioral of genericparitydetector is
begin
process(a)
variable x:std_logic;
begin
x:='0';
for i in 0 to n loop
x:=x xor a(i);
end loop;
y<=x&a;
end process;
end Behavioral;

--conversion of signed std_vector to integer value:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity signedbin_to_int is
port(a:in std_logic_vector(3 downto 0);
n:out integer);
end signedbin_to_int;
architecture beh of signedbin_to_int is
begin
process(a)
variable x:integer;
begin 
x:=0;
for i in 0 to 3 loop
if(a(i)='1') then
x:=x+(2**i);
end if;
end loop;
if(a(3)='1') then 
x:=x-16;
end if;
n<=x;
end process;
end beh;

The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)

--code for ripple subtractor using full adder:
library ieee;
entity ripplesub is
port(a,b: in bit_vector(3 downto 0);
c0:inout bit;
d:out bit_vector(3 downto 0);
cout: out bit);
end ripplesub;

architecture struct of ripplesub is
component fulladder is
port(a,b,cin:in bit;
s,cout:out bit);
end component;
signal c:bit_vector(3 downto 1);
begin
c0<='1';
a1:fulladder port map(a(0),not b(0),c0,d(0),c(1));
a2:fulladder port map(a(1),not b(1),c(1),d(1),c(2));
a3:fulladder port map(a(2),not b(2),c(2),d(2),c(3));
a4:fulladder port map(a(3),not b(3),c(3),d(3),cout);
end struct; 

--component:
library ieee;
entity fulladder is
port(a,b,cin:in bit;
s,cout:out bit);
end fulladder;

architecture dataflow of fulladder is
begin
s<= (a xor b) xor cin;
cout<= (a and b)or (b and cin) or(a and cin);
end dataflow;

The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)

--code for priority encoder using dataflow method:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity priority_encoder is
port( a:in std_logic_vector(7 downto 1);
y:out std_logic_vector(2 downto 0));
end priority_encoder;

architecture Behavioral of priority_encoder is
begin
y(2)<= a(7) or a(6) or a(5)or a(4);
y(1)<= a(7) or a(6) or ((not  a(5)) and (not  a(4)) and (a(3) or  a(2)));
y(0)<= a(7) or ((not a(6)) and (a(5) or ((not a(4)) and (a(3) or ((not a(2)) and a(1))))));
end Behavioral;

--code for priority encoder:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity priority_encoder_when is
port( a:in std_logic_vector(7 downto 1);
y:out std_logic_vector(2 downto 0));
end priority_encoder_when;

architecture Behavioral of priority_encoder_when is
begin
y<="111" when a(7)='1' else
   "110" when a(6)='1' else
"101" when a(5)='1' else
"100" when a(4)='1' else
"011" when a(3)='1' else
"010" when a(2)='1' else
"001" when a(1)='1' else
"000";
end Behavioral;

The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)

--code for counting no of 1's using loop method:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity onesusingloop is
 port(d:in std_logic_vector(9 downto 0);
 count:out integer);
 end onesusingloop;

 architecture beh of onesusingloop is
 begin
 process(d)
 variable x:integer;
 begin
 x:=0;
 for i in 0 to 9 loop
 if(d(i)='1')then
 x:=x+1;
 end if;
 end loop;
 count<=x;
 end process;
 end beh;

The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)

--vhdl code for 16:1 mux using 8:1 :

library IEEE;
entity mux16using8 is
port(d:in bit_vector(15 downto 0);
s:in bit_vector(3 downto 0);
e:in bit;
y:out bit);
end mux16using8;

architecture Behavioral of mux16using8 is
component mux8 is
port(d:in bit_vector(7 downto 0);
e:in bit;
s:in bit_vector(2 downto 0);
y:out bit);
end component;
component mux2 is
port ( d:in bit_vector(1 downto 0);
e,s:in bit;
y:out bit);
end component;
signal m:bit_vector(1 downto 0);
begin
m1:mux8 port map(d(7 downto 0),e,s(2 downto 0),m(0));
m2:mux8 port map(d(15 downto 8),e,s(2 downto 0),m(1));
m3:mux2 port map(m,e,s(3),y);
end Behavioral;

--code for 8 :1 mux:

--code for 4:1 mux:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux4 is
port(d:in std_logic_vector(3 downto 0);
 e:in std_logic;
 s:in std_logic_vector(1 downto 0);
 y: out std_logic);
end mux4;
architecture Behavioral of mux4 is
signal m:std_logic;
begin
with e select
 y<= m when '1',
    '0' when others;
with s select
m<= d(0) when "00",
    d(1) when "01",
d(2) when "10",
d(3) when "11",
'0' when others;
end Behavioral;

The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)

--VHDL code for d-flip flop:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity d_ff is
port(d,rst,sel,clk:in std_logic;
q,qb:out std_logic);
end d_ff;

architecture Behavioral of d_ff is
begin
process
variable x:std_logic:='0';
begin
wait on clk ;
if (clk' event and clk='1') then
if rst='1' then
x:='0';
else
x:=d;
end if;
end if;
q<=x;
qb<=not x;
end process;

end Behavioral;

--VHDL code to convert integer to std_logic_vector:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity int_to_std is
port(a:in integer;
y:out std_logic_vector(15 downto 0));
end int_to_std;

architecture Behavioral of int_to_std is
function int_std(j:integer)
return std_logic_vector is
variable y:std_logic_vector(15 downto 0):=(others=>'0');
variable l:integer:=0;
begin 
l:=j;
while (l>0) loop
for i in 14 downto 0 loop
if(l>=2**i) then
y(i):='1';
l:=l-2**i;
exit;
end if;
end loop;
end loop;
return y;
end int_std;
begin
y<=int_std(a);
end Behavioral;

VHDL code for 4 bit ripple adder:
--main code:
library ieee;
entity bit4ripple_struct is
port(a,b:in bit_vector(3 downto 0);
cin:in bit;
cout:out bit;
s:out bit_vector(3 downto 0));
end bit4ripple_struct;

architecture Behavioral of bit4ripple_struct is
component fulladder is
port(a,b,cin:in bit;
s,cout:out bit);
end component;
signal c:bit_vector(3 downto 1);
begin
a1:fulladder port map(a(0),b(0),cin,s(0),c(1));
a4:fulladder port map(a(1),b(1),c(1),s(1),c(2));
a2:fulladder port map(a(2),b(2),c(2),s(2),c(3));
a3:fulladder port map(a(3),b(3),c(3),s(3),cout);
end Behavioral;

--component code(full adder):

library ieee;
entity fulladder is
port(a,b,cin:in bit;
s,cout:out bit);
end fulladder;

architecture dataflow of fulladder is
begin
s<= (a xor b) xor cin;
cout<= (a and b)or (b and cin) or(a and cin);
end dataflow;

The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)

--VHDL code for Barrel Shifter:

library ieee;
use ieee.std_logic_1164.all;

entity barrel is
port(inp:in std_logic_vector(7 downto 0);
shift:in std_logic_vector(2 downto 0);
outp:out std_logic_vector(7 downto 0));
end barrel;

architecture behaviour of barrel is
begin
process(inp,shift)
variable temp1:std_logic_vector(7 downto 0);
variable temp2:std_logic_vector(7 downto 0);
begin
--1st shifter
if(shift(0)='0') then
temp1:=inp;
else
temp1(0):='0';
for i in 1 to 7 loop
temp1(i):=inp(i-1);
end loop;
end if;

--2nd shifter

if(shift(1)='0') then
temp2:=temp1;
else

for i in 0 to 1 loop
temp2(i):='0';
end loop;
for i in 2 to inp'high loop
temp2(i):=temp1(i-2);
end loop;
end if;


--3rd shifter
if(shift(2)='0') then
outp<=temp2;
else 
for i in 0 to 3 loop
outp(i)<='0';
end loop;
for i in 4 to inp'high loop
outp(i)<=inp(i-4);
end loop;
end if;
end process;
end behaviour;


The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)

--VHDL code for comparator using subtractor:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bit3_comp_add is
port(a,b:in bit_vector(2 downto 0);
cin:in bit;
alb,agb,aeb:out bit);
end bit3_comp_add;

architecture Behavioral of bit3_comp_add is
component full_adder is
port(a,b,cin:in bit;
s,c:out bit);
end component;
signal s,c:bit_vector(2 downto 0);
signal x:bit;
begin
a1: full_adder port map(a(0),(not b(0)),cin,s(0),c(0));
a2: full_adder port map(a(1),(not b(1)),c(0),s(1),c(1));
a3: full_adder port map(a(2),(not b(2)),c(1),s(2),c(2));
agb<=c(2);
x<= s(0) and s(1) and s(2);
alb<= c(2) nor x;
aeb<=x;
end Behavioral; 


--component code:

library IEEE;
entity full_adder is
port(a,b,cin:in bit;
s,c:out bit);
end full_adder;
architecture Behavioral of full_adder is
begin 
s<= a xor b xor cin;
c<=(a and b)or(b and cin) or(cin and a);
end Behavioral; 

The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)

--VHDL code for 4 bit hexadecimal counter

--main code:

library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL; -- Two very useful
use IEEE.STD_LOGIC_UNSIGNED.ALL; -- IEEE libraries

entity hexa is
port(Clk, rst: in std_logic;
 disp_0, disp_1, disp_2, disp_3: out std_logic_vector(6 downto 0));
end hexa;

architecture behavior of hexa is

component Display is
port( num_0: in std_logic_vector(3 downto 0);
  ddisp_0: out std_logic_vector(6 downto 0));
end component;

component tcounter is
port(clk,rst:in std_logic;
q,qbar:inout std_logic_vector(3 downto 0));
end component;

component clk_generator is
Port (input: in std_logic_vector(3 downto 0);
      clock:out std_logic);
end component;

signal count_1,count_2,count_3,count_4: std_logic_vector(3 downto 0);
signal clock1,clock2,clock3:std_logic;
begin
lbl1: tcounter port map (clk,rst,count_1);
 c1:clk_generator port map(count_1,clock1); 
lbl2: tcounter port map (clock1,rst,count_2);
c2:clk_generator port map(count_2,clock2); 
lbl3: tcounter port map (clock2,rst,count_3);
c3:clk_generator port map(count_3,clock3); 
lbl4: tcounter port map (clock3,rst,count_4);
dd_0: Display port map (count_1, disp_0);
dd_1: Display port map (count_2, disp_1);
dd_2: Display port map (count_3, disp_2);
dd_3: Display port map (count_4, disp_3);
end behavior;

--component code:
--t counter:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tcounter is
port(clk,rst:in std_logic;
q,qbar:inout std_logic_vector(3 downto 0));
end tcounter;

architecture Behavioral of tcounter is
component tffl is
port(t,rst,clk:in std_logic;
q,qb:out std_logic);
end component;
signal k,l,m:std_logic;
begin
k<=q(0); 
l<=q(0) and q(1);
m<=q(0) and q(1) and q(2);
a1:tffl port map('1',rst,clk,q(0),qbar(0));
a2:tffl port map(k,rst,clk,q(1),qbar(1));
a3:tffl port map(l,rst,clk,q(2),qbar(2));
a4:tffl port map(m,rst,clk,q(3),qbar(3));
end Behavioral;



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL; -- Two very useful
use IEEE.STD_LOGIC_UNSIGNED.ALL; -- IEEE libraries

entity clk_generator is
Port (input: in std_logic_vector(3 downto 0);
      clock:out std_logic);
end clk_generator;


architecture behavioral of clk_generator is
signal x:std_logic;
begin
process(input,x)
begin
if(input="0000") then 
x<='1';
else 
x<='0';
end if;
end process;
clock<=x; 
end behavioral; 



library ieee;
use ieee.std_logic_1164.all;

entity Display is
port( num_0: in std_logic_vector(3 downto 0);
ddisp_0: out std_logic_vector(6 downto 0));
end Display;

architecture struct of Display is
begin
process (num_0)
begin
case num_0 is
when "0000" => ddisp_0 <= "1000000";
when "0001" => ddisp_0 <= "1111001";
when "0010" => ddisp_0 <= "0100100";
when "0011" => ddisp_0 <= "0110000";
when "0100" => ddisp_0 <= "0011001";
when "0101" => ddisp_0 <= "0010010";
when "0110" => ddisp_0 <= "0000010";
when "0111" => ddisp_0 <= "1111000";
when "1000" => ddisp_0 <= "0000000";
when "1001" => ddisp_0 <= "0010000";
when "1010" => ddisp_0 <= "0001000";
when "1011" => ddisp_0 <= "0000011";
when "1100" => ddisp_0 <= "1000110";
when "1101" => ddisp_0 <= "0100001";
when "1110" => ddisp_0 <= "0000110";
when "1111" => ddisp_0 <= "0001110";
when others=> null;
end case;
end process;
end struct;

The above code has been executed and has been found to have no errors..!  
plz do comment..! thank u..!! :) :)