--code for 4:1 mux:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux4 is
port(d:in std_logic_vector(3 downto 0);
e:in std_logic;
s:in std_logic_vector(1 downto 0);
y: out std_logic);
end mux4;
architecture Behavioral of mux4 is
signal m:std_logic;
begin
with e select
y<= m when '1',
'0' when others;
with s select
m<= d(0) when "00",
d(1) when "01",
d(2) when "10",
d(3) when "11",
'0' when others;
end Behavioral;
The above code has been executed and has been found to have no errors..!
plz do comment..!
thank u..!! :) :)
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