--vhdl code for 16:1 mux using 8:1 :
library IEEE;
entity mux16using8 is
port(d:in bit_vector(15 downto 0);
s:in bit_vector(3 downto 0);
e:in bit;
y:out bit);
end mux16using8;
architecture Behavioral of mux16using8 is
component mux8 is
port(d:in bit_vector(7 downto 0);
e:in bit;
s:in bit_vector(2 downto 0);
y:out bit);
end component;
component mux2 is
port ( d:in bit_vector(1 downto 0);
e,s:in bit;
y:out bit);
end component;
signal m:bit_vector(1 downto 0);
begin
m1:mux8 port map(d(7 downto 0),e,s(2 downto 0),m(0));
m2:mux8 port map(d(15 downto 8),e,s(2 downto 0),m(1));
m3:mux2 port map(m,e,s(3),y);
end Behavioral;
The above code has been executed and has been found to have no errors..!
plz do comment..!
thank u..!! :) :)
plz do comment..!
thank u..!! :) :)
5 comments:
I have written a similar code for 16:1 mux using 4:1 mux. though it has no errors but it does not give the expected results.
actually
Can you post the structural style modelling for the same code
how to write a test bench for this program
How to write a code for 8:1 using 4:1
Post a Comment