--conversion of signed std_vector to integer value:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity signedbin_to_int is
port(a:in std_logic_vector(3 downto 0);
n:out integer);
end signedbin_to_int;
architecture beh of signedbin_to_int is
begin
process(a)
variable x:integer;
begin
x:=0;
for i in 0 to 3 loop
if(a(i)='1') then
x:=x+(2**i);
end if;
end loop;
if(a(3)='1') then
x:=x-16;
end if;
n<=x;
end process;
end beh;
The above code has been executed and has been found to have no errors..!
plz do comment..!
thank u..!! :) :)
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