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Showing posts with label mux. Show all posts
Showing posts with label mux. Show all posts


--code for 8 :1 mux:

library ieee;
entity mux8 is
port(d:in bit_vector(7 downto 0);
e:in bit;
s:in bit_vector(2 downto 0);
y:out bit);
end mux8;

architecture struct of mux8 is
signal m:bit;
begin
with e select
y<='0' when '0',
    m when '1';
with s select
m<=d(0) when "000",
   d(1) when "001",
d(2) when "010",
d(3) when "011",
d(4) when "100",
d(5) when "101",
d(6) when "110",
d(7) when "111";
end struct;

The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)


--code for 4:1 mux:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux4 is
port(d:in std_logic_vector(3 downto 0);
 e:in std_logic;
 s:in std_logic_vector(1 downto 0);
 y: out std_logic);
end mux4;
architecture Behavioral of mux4 is
signal m:std_logic;
begin
with e select
 y<= m when '1',
    '0' when others;
with s select
m<= d(0) when "00",
    d(1) when "01",
d(2) when "10",
d(3) when "11",
'0' when others;
end Behavioral;

The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)

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