--generic parity detector:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity genericparitydetector is
generic(n:integer:=8);
port(a:in std_logic_vector(n downto 0);
y:out std_logic_vector(n+1 downto 0));
end genericparitydetector;
architecture Behavioral of genericparitydetector is
begin
process(a)
variable x:std_logic;
begin
x:='0';
for i in 0 to n loop
x:=x xor a(i);
end loop;
y<=x&a;
end process;
end Behavioral;
The above code has been executed and has been found to have no errors..!
plz do comment..!
thank u..!! :) :)
plz do comment..!
thank u..!! :) :)
1 comments:
1. Write the VHDL code for the Generic Parity Detector whose top-level diagram as shown in following figure. It must provide the output =0 when the number of 1’s in the input vector is even or output=1 otherwise. Write the Test Bench and attach the simulation result showing the outputs result for 4+R1 combinations from all possible combinations of input with a delay of 2 ps (Pico-Seconds) for each combination. (Where R2 is LSD of your Roll Number).
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