--VHDL code for d-flip flop:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity d_ff is
port(d,rst,sel,clk:in std_logic;
q,qb:out std_logic);
end d_ff;
architecture Behavioral of d_ff is
begin
process
variable x:std_logic:='0';
begin
wait on clk ;
if (clk' event and clk='1') then
if rst='1' then
x:='0';
else
x:=d;
end if;
end if;
q<=x;
qb<=not x;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity d_ff is
port(d,rst,sel,clk:in std_logic;
q,qb:out std_logic);
end d_ff;
architecture Behavioral of d_ff is
begin
process
variable x:std_logic:='0';
begin
wait on clk ;
if (clk' event and clk='1') then
if rst='1' then
x:='0';
else
x:=d;
end if;
end if;
q<=x;
qb<=not x;
end process;
end Behavioral;
The above code has been executed and has been found to have no errors..!
plz do comment..!
thank u..!! :) :)
plz do comment..!
thank u..!! :) :)
0 comments:
Post a Comment