--code for ripple subtractor using full adder:
library ieee;
entity ripplesub is
port(a,b: in bit_vector(3 downto 0);
c0:inout bit;
d:out bit_vector(3 downto 0);
cout: out bit);
end ripplesub;
architecture struct of ripplesub is
component fulladder is
port(a,b,cin:in bit;
s,cout:out bit);
end component;
signal c:bit_vector(3 downto 1);
begin
c0<='1';
a1:fulladder port map(a(0),not b(0),c0,d(0),c(1));
a2:fulladder port map(a(1),not b(1),c(1),d(1),c(2));
a3:fulladder port map(a(2),not b(2),c(2),d(2),c(3));
a4:fulladder port map(a(3),not b(3),c(3),d(3),cout);
end struct;
--component:
library ieee;
entity fulladder is
port(a,b,cin:in bit;
s,cout:out bit);
end fulladder;
architecture dataflow of fulladder is
begin
s<= (a xor b) xor cin;
cout<= (a and b)or (b and cin) or(a and cin);
end dataflow;
The above code has been executed and has been found to have no errors..!
plz do comment..!
thank u..!! :) :)
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