--VHDL code to convert integer to std_logic_vector:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity int_to_std is
port(a:in integer;
y:out std_logic_vector(15 downto 0));
end int_to_std;
architecture Behavioral of int_to_std is
function int_std(j:integer)
return std_logic_vector is
variable y:std_logic_vector(15 downto 0):=(others=>'0');
variable l:integer:=0;
begin
l:=j;
while (l>0) loop
for i in 14 downto 0 loop
if(l>=2**i) then
y(i):='1';
l:=l-2**i;
exit;
end if;
end loop;
end loop;
return y;
end int_std;
begin
y<=int_std(a);
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity int_to_std is
port(a:in integer;
y:out std_logic_vector(15 downto 0));
end int_to_std;
architecture Behavioral of int_to_std is
function int_std(j:integer)
return std_logic_vector is
variable y:std_logic_vector(15 downto 0):=(others=>'0');
variable l:integer:=0;
begin
l:=j;
while (l>0) loop
for i in 14 downto 0 loop
if(l>=2**i) then
y(i):='1';
l:=l-2**i;
exit;
end if;
end loop;
end loop;
return y;
end int_std;
begin
y<=int_std(a);
end Behavioral;
The above code has been executed and has been found to have no errors..!
plz do comment..!
thank u..!! :) :)
plz do comment..!
thank u..!! :) :)
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