VHDL code for 4 bit ripple adder:
--main code:
library ieee;
entity bit4ripple_struct is
port(a,b:in bit_vector(3 downto 0);
cin:in bit;
cout:out bit;
s:out bit_vector(3 downto 0));
end bit4ripple_struct;
architecture Behavioral of bit4ripple_struct is
component fulladder is
port(a,b,cin:in bit;
s,cout:out bit);
end component;
signal c:bit_vector(3 downto 1);
begin
a1:fulladder port map(a(0),b(0),cin,s(0),c(1));
a4:fulladder port map(a(1),b(1),c(1),s(1),c(2));
a2:fulladder port map(a(2),b(2),c(2),s(2),c(3));
a3:fulladder port map(a(3),b(3),c(3),s(3),cout);
end Behavioral;
--component code(full adder):
library ieee;
entity fulladder is
port(a,b,cin:in bit;
s,cout:out bit);
end fulladder;
architecture dataflow of fulladder is
begin
s<= (a xor b) xor cin;
cout<= (a and b)or (b and cin) or(a and cin);
end dataflow;
The above code has been executed and has been found to have no errors..!
plz do comment..!
thank u..!! :) :)
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