TechNiPr0

--VHDL code for 4 bit hexadecimal counter

--main code:

library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL; -- Two very useful
use IEEE.STD_LOGIC_UNSIGNED.ALL; -- IEEE libraries

entity hexa is
port(Clk, rst: in std_logic;
 disp_0, disp_1, disp_2, disp_3: out std_logic_vector(6 downto 0));
end hexa;

architecture behavior of hexa is

component Display is
port( num_0: in std_logic_vector(3 downto 0);
  ddisp_0: out std_logic_vector(6 downto 0));
end component;

component tcounter is
port(clk,rst:in std_logic;
q,qbar:inout std_logic_vector(3 downto 0));
end component;

component clk_generator is
Port (input: in std_logic_vector(3 downto 0);
      clock:out std_logic);
end component;

signal count_1,count_2,count_3,count_4: std_logic_vector(3 downto 0);
signal clock1,clock2,clock3:std_logic;
begin
lbl1: tcounter port map (clk,rst,count_1);
 c1:clk_generator port map(count_1,clock1); 
lbl2: tcounter port map (clock1,rst,count_2);
c2:clk_generator port map(count_2,clock2); 
lbl3: tcounter port map (clock2,rst,count_3);
c3:clk_generator port map(count_3,clock3); 
lbl4: tcounter port map (clock3,rst,count_4);
dd_0: Display port map (count_1, disp_0);
dd_1: Display port map (count_2, disp_1);
dd_2: Display port map (count_3, disp_2);
dd_3: Display port map (count_4, disp_3);
end behavior;

--component code:
--t counter:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tcounter is
port(clk,rst:in std_logic;
q,qbar:inout std_logic_vector(3 downto 0));
end tcounter;

architecture Behavioral of tcounter is
component tffl is
port(t,rst,clk:in std_logic;
q,qb:out std_logic);
end component;
signal k,l,m:std_logic;
begin
k<=q(0); 
l<=q(0) and q(1);
m<=q(0) and q(1) and q(2);
a1:tffl port map('1',rst,clk,q(0),qbar(0));
a2:tffl port map(k,rst,clk,q(1),qbar(1));
a3:tffl port map(l,rst,clk,q(2),qbar(2));
a4:tffl port map(m,rst,clk,q(3),qbar(3));
end Behavioral;



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL; -- Two very useful
use IEEE.STD_LOGIC_UNSIGNED.ALL; -- IEEE libraries

entity clk_generator is
Port (input: in std_logic_vector(3 downto 0);
      clock:out std_logic);
end clk_generator;


architecture behavioral of clk_generator is
signal x:std_logic;
begin
process(input,x)
begin
if(input="0000") then 
x<='1';
else 
x<='0';
end if;
end process;
clock<=x; 
end behavioral; 



library ieee;
use ieee.std_logic_1164.all;

entity Display is
port( num_0: in std_logic_vector(3 downto 0);
ddisp_0: out std_logic_vector(6 downto 0));
end Display;

architecture struct of Display is
begin
process (num_0)
begin
case num_0 is
when "0000" => ddisp_0 <= "1000000";
when "0001" => ddisp_0 <= "1111001";
when "0010" => ddisp_0 <= "0100100";
when "0011" => ddisp_0 <= "0110000";
when "0100" => ddisp_0 <= "0011001";
when "0101" => ddisp_0 <= "0010010";
when "0110" => ddisp_0 <= "0000010";
when "0111" => ddisp_0 <= "1111000";
when "1000" => ddisp_0 <= "0000000";
when "1001" => ddisp_0 <= "0010000";
when "1010" => ddisp_0 <= "0001000";
when "1011" => ddisp_0 <= "0000011";
when "1100" => ddisp_0 <= "1000110";
when "1101" => ddisp_0 <= "0100001";
when "1110" => ddisp_0 <= "0000110";
when "1111" => ddisp_0 <= "0001110";
when others=> null;
end case;
end process;
end struct;

The above code has been executed and has been found to have no errors..!  
plz do comment..! thank u..!! :) :)