--VHDL code for transmitting 7 bit data:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
entity datatransmitter is
port(data:in std_logic_vector(6 downto 0);
clk,data_ready:in std_logic;
dout:out std_logic);
end datatransmitter;
architecture Behavioral of datatransmitter is
begin
process(clk,data_ready)
variable x:std_logic_vector(9 downto 0);
variable y:std_logic;
begin
y:=data(0)xor data(1)xor data(2)xor data(3)xor data(4)xor data(5)xor data(6);
if(data_ready='0') then
dout<='0';
x:='1'&data&y&'1';
elsif(clk' event and clk='1') then
dout<=x(9);
x:=x(8 downto 0)&'0';
end if;
end process;
end Behavioral;
The above code has been executed and has been found to have no errors..!
plz do comment..!
thank u..!! :) :)
plz do comment..!
thank u..!! :) :)
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