TechNiPr0

--vhdl code for data receiver using FSM:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fsm_data_reciever is
port(din,clk,rst:in std_logic;
data_out:out std_logic_vector(6 downto 0);
err,valid:out std_logic);
end fsm_data_reciever;

architecture Behavioral of fsm_data_reciever is
type states is (start,dzero,done,dtwo,dthree,dfour,dfive,dsix,parity,stop);
signal pr_state,nx_state:states;
signal d:std_logic_vector(0 to 8);
signal temp: std_logic:='0';
begin

process(rst,clk)
begin
if rst='1' then 
pr_state<=start;
elsif (clk' event and clk='1') then
pr_state<=nx_state;
end if;
end process; 

process(din,pr_state)
begin 
case pr_state is
 when start => 
      if (din='1') then
   nx_state<= dzero;
  else 
   nx_state<= start;
  end if;
 when dzero =>
       d(0)<= din;
       nx_state<=done;
 when done=>
      d(1)<= din;
nx_state<=dtwo;
 when dtwo=>
      d(2)<= din;
nx_state<=dthree;
 when dthree=> 
      d(3)<= din;
nx_state<=dfour;
 when dfour=>
      d(4)<= din;
nx_state<=dfive;
 when dfive=>
      d(5)<= din;
nx_state<=dsix;
 when dsix=>
      d(6)<= din;
nx_state<=parity;
 when parity=>
      d(7)<= din;
nx_state<=stop;
 when stop=>
      d(8)<= din;
temp<=(d(0)xor d(1)xor d(2)xor d(3)xor d(4)xor d(5)xor d(6)xor d(7))or (not d(8));
err<=temp;
valid<=not temp;
if((not temp) ='1') then
data_out<=d(0 to 6);
end if;
nx_state<=start;
      end case;
end process;
end Behavioral;

The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)