--VHDL code for comparator using subtractor:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bit3_comp_add is
port(a,b:in bit_vector(2 downto 0);
cin:in bit;
alb,agb,aeb:out bit);
end bit3_comp_add;
architecture Behavioral of bit3_comp_add is
component full_adder is
port(a,b,cin:in bit;
s,c:out bit);
end component;
signal s,c:bit_vector(2 downto 0);
signal x:bit;
begin
a1: full_adder port map(a(0),(not b(0)),cin,s(0),c(0));
a2: full_adder port map(a(1),(not b(1)),c(0),s(1),c(1));
a3: full_adder port map(a(2),(not b(2)),c(1),s(2),c(2));
agb<=c(2);
x<= s(0) and s(1) and s(2);
alb<= c(2) nor x;
aeb<=x;
end Behavioral;
--component code:
library IEEE;
entity full_adder is
port(a,b,cin:in bit;
s,c:out bit);
end full_adder;
architecture Behavioral of full_adder is
begin
s<= a xor b xor cin;
c<=(a and b)or(b and cin) or(cin and a);
end Behavioral;
The above code has been executed and has been found to have no errors..!
plz do comment..!
thank u..!! :) :)
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