TechNiPr0

To put it simply, I think people expected a LOT more from BD, myself included.

Sandy Bridge and the newly introduced Ivy Bridge has great single threaded performance and good (2500K) to great (2600K) Multi-Threading performance.

With BD you have a massive trade-off in single/lightly threaded apps just to approach 2600K levels of MT performance. Its even slower than Phenon II in IPC!. I expected a 2 billion transistor budget chip to perform a bit better vs it's own companies 0.9 billion transistor chip. Given that it was a next gen design!.

Finally, just addressing the point of gaming, to an extent its true that most games are GPU bound, but there are still CPU bound games out there like SC2. Also there are enthusiasts are also the ones sprouting multi GPU setups, where CPU speed does make a tangible difference compared with single GPU setups.


If the FX-8150 were priced the same as the i5-2500K, it would be a better value unless you were primarily a single-threaded application user. It's a harder sell at its current pricing. For gaming, it would be a moot point since anyone using these chips is gaming at 1080p and is GPU-bound, not CPU-bound. As the prices align now, the FX-8150 is not a particularly compelling value, unless you primarily use heavily-multithreaded applications.

Yes, it costs less than the i7-2600K and either rivals or bests it in modern multi-threaded titles. Bulldozer clearly illustrates how a chip can absolutely dominate in one type of task (see AnandTech's 7-Zip benchmark) while downright stinking for another task (see any single-threaded application benchmark). Five years ago, everyone benefited from moving to a dual core from a single core. Today, not many people will benefit from moving from four to eight cores. "What are you going to do with your computer?" is now more important than ever in determining what CPU will suit you best.

Are there really so many enthusiasts here and elsewhere who are so myopic they fail to see the flagship Bulldozer SKU beating the flagship Core SKU in a few relevant, real world applications? Are there really so many failing to see that while Bulldozer did not wrest the performance crown from Intel, it finally brings some semblance of competition to the i5-2500 and i7-2600? Again, some people are going to benefit from Bulldozer over the high-end Core SKUs. But not everyone.

Finally, where are the reviews of the $165 FX-6100 vs. the $180 i5-2300? ...What about the $115 FX-4100 vs. the $125 i3-2100? First, you can actually overclock the AMD chips. You can't overclock the i5-2300 nor the i3-2100. Secondly, reviews have made it very clear that Turbo Core in the Bulldozer CPUs works really well - better than it did in the 6-core Thubans, and better than Intel's Turbo Boost. What effects does this have in typical real-world usage scenarios given the i5-2300's comparatively anemic and i3-2100's non-existent Turbo Boost? There are a lot more people who drop <$200 than >$200 on CPUs - and right now, do we have definitive knowledge of the specific, relevant comparisons I mentioned? Why would anyone dismiss an entire architecture when really all we know is how its high-end compares to the competition's high end?

--generic parity detector:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity genericparitydetector is
generic(n:integer:=8);
port(a:in std_logic_vector(n downto 0);
y:out std_logic_vector(n+1 downto 0));
end genericparitydetector;

architecture Behavioral of genericparitydetector is
begin
process(a)
variable x:std_logic;
begin
x:='0';
for i in 0 to n loop
x:=x xor a(i);
end loop;
y<=x&a;
end process;
end Behavioral;

--conversion of signed std_vector to integer value:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity signedbin_to_int is
port(a:in std_logic_vector(3 downto 0);
n:out integer);
end signedbin_to_int;
architecture beh of signedbin_to_int is
begin
process(a)
variable x:integer;
begin 
x:=0;
for i in 0 to 3 loop
if(a(i)='1') then
x:=x+(2**i);
end if;
end loop;
if(a(3)='1') then 
x:=x-16;
end if;
n<=x;
end process;
end beh;

The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)

--code for ripple subtractor using full adder:
library ieee;
entity ripplesub is
port(a,b: in bit_vector(3 downto 0);
c0:inout bit;
d:out bit_vector(3 downto 0);
cout: out bit);
end ripplesub;

architecture struct of ripplesub is
component fulladder is
port(a,b,cin:in bit;
s,cout:out bit);
end component;
signal c:bit_vector(3 downto 1);
begin
c0<='1';
a1:fulladder port map(a(0),not b(0),c0,d(0),c(1));
a2:fulladder port map(a(1),not b(1),c(1),d(1),c(2));
a3:fulladder port map(a(2),not b(2),c(2),d(2),c(3));
a4:fulladder port map(a(3),not b(3),c(3),d(3),cout);
end struct; 

--component:
library ieee;
entity fulladder is
port(a,b,cin:in bit;
s,cout:out bit);
end fulladder;

architecture dataflow of fulladder is
begin
s<= (a xor b) xor cin;
cout<= (a and b)or (b and cin) or(a and cin);
end dataflow;

The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)

--code for priority encoder using dataflow method:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity priority_encoder is
port( a:in std_logic_vector(7 downto 1);
y:out std_logic_vector(2 downto 0));
end priority_encoder;

architecture Behavioral of priority_encoder is
begin
y(2)<= a(7) or a(6) or a(5)or a(4);
y(1)<= a(7) or a(6) or ((not  a(5)) and (not  a(4)) and (a(3) or  a(2)));
y(0)<= a(7) or ((not a(6)) and (a(5) or ((not a(4)) and (a(3) or ((not a(2)) and a(1))))));
end Behavioral;

--code for priority encoder:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity priority_encoder_when is
port( a:in std_logic_vector(7 downto 1);
y:out std_logic_vector(2 downto 0));
end priority_encoder_when;

architecture Behavioral of priority_encoder_when is
begin
y<="111" when a(7)='1' else
   "110" when a(6)='1' else
"101" when a(5)='1' else
"100" when a(4)='1' else
"011" when a(3)='1' else
"010" when a(2)='1' else
"001" when a(1)='1' else
"000";
end Behavioral;

The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)

--code for counting no of 1's using loop method:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity onesusingloop is
 port(d:in std_logic_vector(9 downto 0);
 count:out integer);
 end onesusingloop;

 architecture beh of onesusingloop is
 begin
 process(d)
 variable x:integer;
 begin
 x:=0;
 for i in 0 to 9 loop
 if(d(i)='1')then
 x:=x+1;
 end if;
 end loop;
 count<=x;
 end process;
 end beh;

The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)

--vhdl code for 16:1 mux using 8:1 :

library IEEE;
entity mux16using8 is
port(d:in bit_vector(15 downto 0);
s:in bit_vector(3 downto 0);
e:in bit;
y:out bit);
end mux16using8;

architecture Behavioral of mux16using8 is
component mux8 is
port(d:in bit_vector(7 downto 0);
e:in bit;
s:in bit_vector(2 downto 0);
y:out bit);
end component;
component mux2 is
port ( d:in bit_vector(1 downto 0);
e,s:in bit;
y:out bit);
end component;
signal m:bit_vector(1 downto 0);
begin
m1:mux8 port map(d(7 downto 0),e,s(2 downto 0),m(0));
m2:mux8 port map(d(15 downto 8),e,s(2 downto 0),m(1));
m3:mux2 port map(m,e,s(3),y);
end Behavioral;

--code for 8 :1 mux:

--code for 4:1 mux:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux4 is
port(d:in std_logic_vector(3 downto 0);
 e:in std_logic;
 s:in std_logic_vector(1 downto 0);
 y: out std_logic);
end mux4;
architecture Behavioral of mux4 is
signal m:std_logic;
begin
with e select
 y<= m when '1',
    '0' when others;
with s select
m<= d(0) when "00",
    d(1) when "01",
d(2) when "10",
d(3) when "11",
'0' when others;
end Behavioral;

The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)

--VHDL code for d-flip flop:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity d_ff is
port(d,rst,sel,clk:in std_logic;
q,qb:out std_logic);
end d_ff;

architecture Behavioral of d_ff is
begin
process
variable x:std_logic:='0';
begin
wait on clk ;
if (clk' event and clk='1') then
if rst='1' then
x:='0';
else
x:=d;
end if;
end if;
q<=x;
qb<=not x;
end process;

end Behavioral;

--VHDL code to convert integer to std_logic_vector:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity int_to_std is
port(a:in integer;
y:out std_logic_vector(15 downto 0));
end int_to_std;

architecture Behavioral of int_to_std is
function int_std(j:integer)
return std_logic_vector is
variable y:std_logic_vector(15 downto 0):=(others=>'0');
variable l:integer:=0;
begin 
l:=j;
while (l>0) loop
for i in 14 downto 0 loop
if(l>=2**i) then
y(i):='1';
l:=l-2**i;
exit;
end if;
end loop;
end loop;
return y;
end int_std;
begin
y<=int_std(a);
end Behavioral;

VHDL code for 4 bit ripple adder:
--main code:
library ieee;
entity bit4ripple_struct is
port(a,b:in bit_vector(3 downto 0);
cin:in bit;
cout:out bit;
s:out bit_vector(3 downto 0));
end bit4ripple_struct;

architecture Behavioral of bit4ripple_struct is
component fulladder is
port(a,b,cin:in bit;
s,cout:out bit);
end component;
signal c:bit_vector(3 downto 1);
begin
a1:fulladder port map(a(0),b(0),cin,s(0),c(1));
a4:fulladder port map(a(1),b(1),c(1),s(1),c(2));
a2:fulladder port map(a(2),b(2),c(2),s(2),c(3));
a3:fulladder port map(a(3),b(3),c(3),s(3),cout);
end Behavioral;

--component code(full adder):

library ieee;
entity fulladder is
port(a,b,cin:in bit;
s,cout:out bit);
end fulladder;

architecture dataflow of fulladder is
begin
s<= (a xor b) xor cin;
cout<= (a and b)or (b and cin) or(a and cin);
end dataflow;

The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)

--VHDL code for Barrel Shifter:

library ieee;
use ieee.std_logic_1164.all;

entity barrel is
port(inp:in std_logic_vector(7 downto 0);
shift:in std_logic_vector(2 downto 0);
outp:out std_logic_vector(7 downto 0));
end barrel;

architecture behaviour of barrel is
begin
process(inp,shift)
variable temp1:std_logic_vector(7 downto 0);
variable temp2:std_logic_vector(7 downto 0);
begin
--1st shifter
if(shift(0)='0') then
temp1:=inp;
else
temp1(0):='0';
for i in 1 to 7 loop
temp1(i):=inp(i-1);
end loop;
end if;

--2nd shifter

if(shift(1)='0') then
temp2:=temp1;
else

for i in 0 to 1 loop
temp2(i):='0';
end loop;
for i in 2 to inp'high loop
temp2(i):=temp1(i-2);
end loop;
end if;


--3rd shifter
if(shift(2)='0') then
outp<=temp2;
else 
for i in 0 to 3 loop
outp(i)<='0';
end loop;
for i in 4 to inp'high loop
outp(i)<=inp(i-4);
end loop;
end if;
end process;
end behaviour;


The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)