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Best Youtube Video downloader :

Lots and lots of people prefer youtube rather than any other website for watching the newly released trailer, video songs and even to get tutorials to learn. But rather many still aren't able to download, and few finding out the ways to get those videos stored in your hard-disk.
Therefore the below are three ways to download youtube videos:

  1. keepvid.com 
 Obviously many would have by now got to know about the website keepvid.com where you just need to 
  paste the link as shown in below image and click on download.
 now you'll be offered the video you wanted in different format and size. Choose the one best for you and click it .
2. Using Internet Download manager:
 This is a downloader which is useful for downloading videos from any website.
 Get this installed from here : internetdownloadmanager . Once done installing this whenever you view a video a small dialog box appears clicking over which you'll be able to download the video you are viewing.
This is awesome it works for almost all of the websites. But you wont be able to choose the format and the size.

3. best video downloader :

This downloader is just applicable to youtube . But still its the best for downloading youtube videos. I loved it a lot. To download it click on this link: bestvideodownloader download 
You need not migrate to any other website to download youtube videos. It'll give you variety of formats to download and a sample picture is shown in the above image. 

 Enjoy downloading!!

Plz do comment!!

If more info is required ,  please do ask for it to be published through comment or by mailing to the below address

 jazzamd786@gmail.com . I would be glad to help u. 

thank u..!! :) :)

Wonder how an Earphone or Headphone Works??

Its working is quite similar to that of speakers. Here we don't need any amplifiers which we employ in case of speakers. We all might know that its just because we don't need to produce any big sound as we place it close to our ears and the sound produced is more than enough to hear to our favourite music. The earphone is a delicate thing which most people use daily to entertain them. Its kinda delicate structure and that's why more often we see that our earphone's get changed atleast once a year.

 Well the earphone jack plays an important role in extracting different signals required for its smooth operation. A normal earphone jack (also called TRS connector) has three parts:
  • Tip
  • Ring 
  • Sleeve
The below image will help you in understanding even better as to which positions of the jack are we referring to.


This TRS connector has three wires attached to it, one for the ground which is passed to both left and right earpiece, and other two are signal carrying wires to left and right earpiece respectively. Now hope everyone got it how is it that sometimes you hear to drum beats in one and simultaneously a different music in other,this is how it all happens, truly awesome.

 Tip of the connector is connected to wire carrying audio equivalent electrical signals to left earpiece while the
Ring connects to the right earpiece and so the sleeve is obviously connected to the ground.
Each of three parts are insulated from one another which can be seen in above picture (here a black insulator separates them from one another). Actually the construction of this connector is as follows,
Firsly a thin rod is taken which has a bulged corner shown in image as TIP and over its rest narrow part an insulator is placed which is again covered by an hollow medium length cylindrical shaped conductor which is referred as SLEEVE. Over the top end of the sleeve which is narrower an insulator is again placed and surrounded finally by the next conductor called as RING.

 The signal carrying wires carry signals to respective earpiece. Both the earpiece have same construction.


The below figure shows how the back connections of an earpiece, where both the wires are connected to the driver unit. This driver unit is in turn connected to the voice coil.


The above picture  shows an earpiece with its top rubbery hollow cover removed. Here we see a metallic plate  over which there comes a net(mesh) covering which prevents unwanted material or dust from entering into the working bottom of the earphone as it could cause an unwanted change in the working of the earpiece and thereby annoy us. The voice coil and the diaphragm is shown. Diaphragm used here is a very thin plastic film and attached to it is the voice coil (copper coil wound with certain number of turns). This copper coil is placed in a region where it surrounds the permanent magnet. When electrical signal pass through the device to the earpiece through signal carrying wires, it is passed on to the voice coil. since these electrical signal is varying proportional to the audio it causes a current flow through the voice coil to be changing accordingly and since we know that a current carrying conductor produces magnetic field there results a varying magnetic field  due to varying current. Since there is a permanent magnet which has its magnetic field around now gets into interaction with the magnetic field created by the voice coil results into a force of attraction or repulsion depending on the current flow in the voice coil, and hence this varying force causes diaphragm attached to the voice coil to vibrate accordingly disturbing the air particles closer to it . This variation then propagates to our ears and gets sensed by the eardrum. So this is how a earphone works!! 

Plz do comment!!

 If more info is required about the working of any other please do ask for it to be published through comment or by mailing to the below address

  jazzamd786@gmail.com . I would be glad to help u. 

thank u..!! :) :)


--VHDL code for 2421 counter using T Flipflop
--main code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tcounter2421 is
port(clk,rst:in std_logic;
q,qbar:inout std_logic_vector(3 downto 0));
end tcounter2421;

architecture Behavioral of tcounter2421 is
component tffl is
port(t,rst,clk:in std_logic;
q,qb:out std_logic);
end component;
signal k,l,m:std_logic;
begin 
k<=q(0)and ((not q(2))or (not q(1)) or q(3));
l<=q(0) and (((not q(2)) and q(1))or q(3));
m<=q(1) and q(2) and q(0);
a1:tffl port map('1',rst,clk,q(0),qbar(0));
a2:tffl port map(k,rst,clk,q(1),qbar(1));
a3:tffl port map(l,rst,clk,q(2),qbar(2));
a4:tffl port map(m,rst,clk,q(3),qbar(3));
end Behavioral;


--t flip flop:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tffl is
port(t,rst,clk:in std_logic;
q,qb:out std_logic);
end tffl;

architecture Behavioral of tffl is
begin
process
variable x:std_logic:='0';
begin
wait on clk ;
if (clk' event and clk='1') then
if rst='1' then
x:='0';
elsif t='1' then
x:=not x;
else
x:=x;
end if;
end if;
q<=x;
qb<=not x;
end process;
end Behavioral;

 The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)

what is a "GEOPHONE" ?? might be the question tumbling in your mind! 

  Geophone is a device which gives electrical output corresponding to the ground movement i.e.,converts seismic energy inputs into electrical voltage a easy to measure and record quantity. 
    Its derived from Greek word, 'Geo' means 'Earth' and 'phone' means 'sound'.

        It  is classified to be a passive device responding to ground displacement which is proportional to the Geophone velocity.

  Similar to this we ground based equipment we have similar for water called as 'HYDROPHONE' !!

Know how it functions ?? and know its importance??

      Above diagram might have given you bit clue as how it works and how its build up!!

     The active element is a block (a mass) nonconducting, whirled by a copper or any good conducting wire.
Active element is suspended using a spring in region enclosed by magnet.This magnet is fixed to the earth using a long spine fixed to it to attach firmly to ground. We all know that any object at rest continues to be at rest until a sufficient force is applied to move it. similarly here when the ground moves the entire configuration moves except the mass which is freely suspended due to inertia and hence we get relative motion between the magnet and the coil and hence output voltage is generated which is proportional to the ground velocity since the magnetic flux changes at a rate equal to the ground velocity. The output can be further amplified to and the setup can be made more precise since even small variations can be recorded. Due to electrical output it is easy to store the data or to process it to any other form.

     Nowadays this setup has been modified to give highly accurate measurement. MEMS (microelectromechanical system) technology that uses a feedback circuit to maintain the position of the small piece of silicon and are basically used to respond to acceleration. They have much higher noise level and hence  are only used for strong motion and active seismic application. 

     Geophone has frequency response similar to the harmonic oscillator. Geophone's are normally constrained to respond to only single dimension variation. 

     Reflection seismology makes majority use of Geophone to record energy waves reflected by subsurface geology i.e., vertical motion is monitored.  Many a times these vertical waves are destroyed by strong horizontally transmitted wave (known as ground roll) which generate vertical motion. This is avoide using them in arrays and tuned to wavelength of ground roll due to which these dominant noise signals are attenuated and  weaker data signals are recorded. 
   
    Passive Geophones are typically very sensitive and thus used in measuring distant tremors. 

Interested to know more abt the recent geophone's manufactured visit www.geophone.com
 
 ---keep visting to know more about many other unknown and known devices. Thankyou
Send your feedback to jazzamd786@gmail.com and help improve!!


To put it simply, I think people expected a LOT more from BD, myself included.

 Sandy Bridge and the newly introduced Ivy Bridge has great single threaded performance and good (2500K) to great (2600K) Multi-Threading performance.

 With BD you have a massive trade-off in single/lightly threaded apps just to approach 2600K levels of MT performance. Its even slower than Phenon II in IPC!. I expected a 2 billion transistor budget chip to perform a bit better vs it's own companies 0.9 billion transistor chip. Given that it was a next gen design!.

 Finally, just addressing the point of gaming, to an extent its true that most games are GPU bound, but there are still CPU bound games out there like SC2. Also there are enthusiasts are also the ones sprouting multi GPU setups, where CPU speed does make a tangible difference compared with single GPU setups.
If the FX-8150 were priced the same as the i5-2500K, it would be a better value unless you were primarily a single-threaded application user. It's a harder sell at its current pricing. For gaming, it would be a moot point since anyone using these chips is gaming at 1080p and is GPU-bound, not CPU-bound. As the prices align now, the FX-8150 is not a particularly compelling value, unless you primarily use heavily-multithreaded applications.

 Yes, it costs less than the i7-2600K and either rivals or bests it in modern multi-threaded titles. Bulldozer clearly illustrates how a chip can absolutely dominate in one type of task (see AnandTech's 7-Zip benchmark) while downright stinking for another task (see any single-threaded application benchmark). Five years ago, everyone benefited from moving to a dual core from a single core. Today, not many people will benefit from moving from four to eight cores. "What are you going to do with your computer?" is now more important than ever in determining what CPU will suit you best.

 Are there really so many enthusiasts here and elsewhere who are so myopic they fail to see the flagship Bulldozer SKU beating the flagship Core SKU in a few relevant, real world applications? Are there really so many failing to see that while Bulldozer did not wrest the performance crown from Intel, it finally brings some semblance of competition to the i5-2500 and i7-2600? Again, some people are going to benefit from Bulldozer over the high-end Core SKUs. But not everyone.

 Finally, where are the reviews of the $165 FX-6100 vs. the $180 i5-2300? ...What about the $115 FX-4100 vs. the $125 i3-2100? First, you can actually overclock the AMD chips. You can't overclock the i5-2300 nor the i3-2100. Secondly, reviews have made it very clear that Turbo Core in the Bulldozer CPUs works really well - better than it did in the 6-core Thubans, and better than Intel's Turbo Boost. What effects does this have in typical real-world usage scenarios given the i5-2300's comparatively anemic and i3-2100's non-existent Turbo Boost? There are a lot more people who drop <$200 than >$200 on CPUs - and right now, do we have definitive knowledge of the specific, relevant comparisons I mentioned? Why would anyone dismiss an entire architecture when really all we know is how its high-end compares to the competition's high end?


--generic parity detector:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity genericparitydetector is
generic(n:integer:=8);
port(a:in std_logic_vector(n downto 0);
y:out std_logic_vector(n+1 downto 0));
end genericparitydetector;

 architecture Behavioral of genericparitydetector is
begin
process(a)
variable x:std_logic;
begin
x:='0';
for i in 0 to n loop
x:=x xor a(i);
end loop;
y<=x&a;
end process;
end Behavioral;

The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :) 


--conversion of signed std_vector to integer value:

 library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity signedbin_to_int is
port(a:in std_logic_vector(3 downto 0);
n:out integer);
end signedbin_to_int;
architecture beh of signedbin_to_int is
begin
process(a)
variable x:integer;
begin 
x:=0;
for i in 0 to 3 loop
if(a(i)='1') then
x:=x+(2**i);
end if;
end loop;
if(a(3)='1') then 
x:=x-16;
end if;
n<=x;
end process;
end beh;

 The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)


--code for ripple subtractor using full adder:
library ieee;
entity ripplesub is
port(a,b: in bit_vector(3 downto 0);
c0:inout bit;
d:out bit_vector(3 downto 0);
cout: out bit);
end ripplesub;

 architecture struct of ripplesub is
component fulladder is
port(a,b,cin:in bit;
s,cout:out bit);
end component;
signal c:bit_vector(3 downto 1);
begin
c0<='1';
a1:fulladder port map(a(0),not b(0),c0,d(0),c(1));
a2:fulladder port map(a(1),not b(1),c(1),d(1),c(2));
a3:fulladder port map(a(2),not b(2),c(2),d(2),c(3));
a4:fulladder port map(a(3),not b(3),c(3),d(3),cout);
end struct; 

 --component:
library ieee;
entity fulladder is
port(a,b,cin:in bit;
s,cout:out bit);
end fulladder;

 architecture dataflow of fulladder is
begin
s<= (a xor b) xor cin;
cout<= (a and b)or (b and cin) or(a and cin);
end dataflow;

 The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)


--code for priority encoder using dataflow method:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

 entity priority_encoder is
port( a:in std_logic_vector(7 downto 1);
y:out std_logic_vector(2 downto 0));
end priority_encoder;

 architecture Behavioral of priority_encoder is
begin
y(2)<= a(7) or a(6) or a(5)or a(4);
y(1)<= a(7) or a(6) or ((not  a(5)) and (not  a(4)) and (a(3) or  a(2)));
y(0)<= a(7) or ((not a(6)) and (a(5) or ((not a(4)) and (a(3) or ((not a(2)) and a(1))))));
end Behavioral;

The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)


--code for priority encoder:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

 entity priority_encoder_when is
port( a:in std_logic_vector(7 downto 1);
y:out std_logic_vector(2 downto 0));
end priority_encoder_when;

 architecture Behavioral of priority_encoder_when is
begin
y<="111" when a(7)='1' else
   "110" when a(6)='1' else
"101" when a(5)='1' else
"100" when a(4)='1' else
"011" when a(3)='1' else
"010" when a(2)='1' else
"001" when a(1)='1' else
"000";
end Behavioral;

 The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)


--code for counting no of 1's using loop method:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity onesusingloop is
 port(d:in std_logic_vector(9 downto 0);
 count:out integer);
 end onesusingloop;

 architecture beh of onesusingloop is
 begin
 process(d)
 variable x:integer;
 begin
 x:=0;
 for i in 0 to 9 loop
 if(d(i)='1')then
 x:=x+1;
 end if;
 end loop;
 count<=x;
 end process;
 end beh;

 The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)


--vhdl code for 16:1 mux using 8:1 :

library IEEE;
entity mux16using8 is
port(d:in bit_vector(15 downto 0);
s:in bit_vector(3 downto 0);
e:in bit;
y:out bit);
end mux16using8;

 architecture Behavioral of mux16using8 is
component mux8 is
port(d:in bit_vector(7 downto 0);
e:in bit;
s:in bit_vector(2 downto 0);
y:out bit);
end component;
component mux2 is
port ( d:in bit_vector(1 downto 0);
e,s:in bit;
y:out bit);
end component;
signal m:bit_vector(1 downto 0);
begin
m1:mux8 port map(d(7 downto 0),e,s(2 downto 0),m(0));
m2:mux8 port map(d(15 downto 8),e,s(2 downto 0),m(1));
m3:mux2 port map(m,e,s(3),y);
end Behavioral;

The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)


--code for 8 :1 mux:

library ieee;
entity mux8 is
port(d:in bit_vector(7 downto 0);
e:in bit;
s:in bit_vector(2 downto 0);
y:out bit);
end mux8;

architecture struct of mux8 is
signal m:bit;
begin
with e select
y<='0' when '0',
    m when '1';
with s select
m<=d(0) when "000",
   d(1) when "001",
d(2) when "010",
d(3) when "011",
d(4) when "100",
d(5) when "101",
d(6) when "110",
d(7) when "111";
end struct;

 The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)


--code for 4:1 mux:

 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux4 is
port(d:in std_logic_vector(3 downto 0);
 e:in std_logic;
 s:in std_logic_vector(1 downto 0);
 y: out std_logic);
end mux4;
architecture Behavioral of mux4 is
signal m:std_logic;
begin
with e select
 y<= m when '1',
    '0' when others;
with s select
m<= d(0) when "00",
    d(1) when "01",
d(2) when "10",
d(3) when "11",
'0' when others;
end Behavioral;

 The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)

--VHDL code for d-flip flop:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity d_ff is
port(d,rst,sel,clk:in std_logic;
q,qb:out std_logic);
end d_ff;

 architecture Behavioral of d_ff is
begin
process
variable x:std_logic:='0';
begin
wait on clk ;
if (clk' event and clk='1') then
if rst='1' then
x:='0';
else
x:=d;
end if;
end if;
q<=x;
qb<=not x;
end process;

 end Behavioral;


The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)


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