--vhdl code for leading one's in structural style:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity leading1 is
port(a:in std_logic_vector(4 downto 0);
count:out integer);
end leading1;
architecture Behavioral of leading1 is
signal b,c,d,x:integer;
begin
with a select
count<=x+1 when "11111",
x when others;
with a(4 downto 1) select
x<=b+1 when "1111",
b when others;
with a(4 downto 2) select
b<= c+1 when "111",
c when others;
with a(4 downto 3) select
c<= d+1 when "11",
d when others;
with a(4) select
d <= 1 when '1',
0 when others;
end Behavioral;
The above code has been executed and has been found to have no errors..! plz do comment..!thank u..!! :) :)
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