--3 bit comparator using subtractor:
--code for full subtractor:
entity bit3_comp_subt is
port(a,b:in bit_vector(2 downto 0);
bin:in bit;
aeb,agb,alb:out bit);
end bit3_comp_subt;
architecture Behavioral of bit3_comp_subt is
component fullsubtractor is
port(a,b,bin:in bit;
d,bout:out bit);
end component;
signal e:bit_vector(1 downto 0);
signal m,n,o,p,bout:bit;
signal d: bit_vector(2 downto 0);
begin
s1: fullsubtractor port map(a(0),b(0),bin,d(0),e(0));
s2: fullsubtractor port map(a(1),b(1),e(0),d(1),e(1));
s3: fullsubtractor port map(a(2),b(2),e(1),d(2),bout);
aeb<= m;
m<=not (d(0) or d(1) or d(2));
agb<= m nor bout;
alb<=bout;
end Behavioral;
The above code has been executed and has been found to have no errors..! plz do comment..!
thank u..!! :) :)
--code for full subtractor:
library ieee;
entity fullsubtractor is
port(a,b,bin:in bit;
d,bout:out bit);
end fullsubtractor;
architecture dataflow of fullsubtractor is
begin
d<=a xor b xor bin;
bout<=((not a)and(b or bin))or(b and bin);
end dataflow;
--code for 3 bit comparator:
entity bit3_comp_subt is
port(a,b:in bit_vector(2 downto 0);
bin:in bit;
aeb,agb,alb:out bit);
end bit3_comp_subt;
architecture Behavioral of bit3_comp_subt is
component fullsubtractor is
port(a,b,bin:in bit;
d,bout:out bit);
end component;
signal e:bit_vector(1 downto 0);
signal m,n,o,p,bout:bit;
signal d: bit_vector(2 downto 0);
begin
s1: fullsubtractor port map(a(0),b(0),bin,d(0),e(0));
s2: fullsubtractor port map(a(1),b(1),e(0),d(1),e(1));
s3: fullsubtractor port map(a(2),b(2),e(1),d(2),bout);
aeb<= m;
m<=not (d(0) or d(1) or d(2));
agb<= m nor bout;
alb<=bout;
end Behavioral;
The above code has been executed and has been found to have no errors..! plz do comment..!
thank u..!! :) :)
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