TechNiPr0

--vhdl code for 16 to 1 mux using for generate.

--code for component : 4 to 1 mux. 


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux_4 is
port(d:in std_logic_vector(3 downto 0);
 e:in std_logic;
 s:in std_logic_vector(1 downto 0);
 y: out std_logic);
end mux_4;
architecture Behavioral of mux_4 is
signal m:std_logic;
begin
with e select
 y<= m when '1',
    '0' when others;
with s select
m<= d(0) when "00",
    d(1) when "01",
d(2) when "10",
d(3) when "11",
'0' when others;
end Behavioral;


--main code..


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity genmux is
port(d:in std_logic_vector(15 downto 0);
s:in std_logic_vector(3 downto 0);
y:out std_logic);
end genmux;
architecture behavioural of genmux is
component mux_4 is
port(d:in std_logic_vector(3 downto 0);
s:in std_logic_vector(1 downto 0);
y:out std_logic);
end component; 
signal x:std_logic_vector(3 downto 0);
begin 
a2:for i in 0 to 3 generate
ai:mux_4 port map(d((((i+1)*4)-1) downto (i*4)),s(1 downto 0),x(i));
end generate;
a5:mux_4 port map(x(3 downto 0),s(3 downto 2),y);
end behavioural;

The above code has been executed and has been found to have no errors..!  plz do comment..!
thank u..!! :) :)