vhdl code for leading 1's in dataflow style
library ieee;
entity leading1s is
port(a:in bit_vector(3 downto 0);
y:out bit_vector(2 downto 0));
end leading1s;
architecture arch of leading1s is
begin
y(2)<=(a(3) and a(2) and a(1) and a(0));
y(1)<=(a(3) and a(2) and (a(1) xor a(0)));
y(0)<=((a(3) and (not a(2))) or (a(3) and (not a(0)) and a(1)));
end arch;
The above code has been executed and has been found to
have no errors..! plz do comment..!
thank u..!! :) :)
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