--vhdl code for counter using jk flip flop as component:
--code for jk flip flop (component):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity jkffl is
port(j,k,rst,clk:in std_logic;
q,qbar:out std_logic);
end jkffl;
architecture Behavioral of jkffl is
begin
process(clk,j,k,rst)
variable x:std_logic:='0';
begin
if (clk' event and clk='1') then
case rst is
when '1'=> x:='0';
when '0'=> if (j='0' and k='0')then
x:=x;
elsif(j='0' and k='1') then
x:='0';
elsif (j='1' and k='0') then
x:='1';
elsif(j='1' and k='1')then
x:=not x;
end if;
when others=> null;
end case;
end if;
q<= x;
qbar<= not x;
end process;
end Behavioral;
--main code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity jkcounter is
port(clk,rst:in std_logic;
q,qb:inout std_logic_vector(3 downto 0));
end jkcounter;
architecture arch of jkcounter is
component jkffl is
port(j,k,rst,clk:in std_logic;
q,qbar:out std_logic);
end component;
signal k,l,m:std_logic;
begin
k<=q(0);
l<=q(0) and q(1);
m<=q(0) and q(1) and q(2);
a1:jkffl port map('1','1',rst,clk,q(0),qb(0));
a2:jkffl port map(k,k,rst,clk,q(1),qb(1));
a3:jkffl port map(l,l,rst,clk,q(2),qb(2));
a4:jkffl port map(m,m,rst,clk,q(3),qb(3));
end arch;
--for up counter consider the output at q
--for down counter consider the output at qb.
The above code has been executed and has been found to have no errors..! plz do comment..!
thank u..!! :) : )
5 comments:
Thank u soo much
hello!
I wanted to know how do you simulate it!
i MEANT THE INITIAL VALUES.
code of j error
hello can u plz send me the logic diagram
Code for down counter
Post a Comment