TechNiPr0

--vhdl code for counting number of one's using structural style:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity noof1 is
port(a:in std_logic_vector(4 downto 0);
count:out integer);
end noof1;

architecture structural of noof1 is
signal b,c,d,x:integer;
begin
with a(0) select
count<=x+1 when '1',
       x when others;
with a(1) select
  x<=b+1 when '1',
      b when others;
with a(2) select  
b<= c+1 when '1',
   c when others;
with a(3) select  
   c<= d+1 when '1',
    d when others;
with a(4) select
d<= 1 when '1',
    0 when others;
end structural;

The above code has been executed and has been found to have no errors..!  plz do comment..!thank u..!! :) :)

--vhdl code to count number of 1's using behavioral:


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity one_counter is
port(a:in std_logic_vector(9 downto 0);
count:out integer);
end one_counter; 
architecture Behavioral of one_counter is
begin

process(a)
variable c: integer;
begin
c:=0;
a1:for i in 0 to 9 loop
if(a(i)='1')then
c:=c+1;
end if; 
end loop a1;
count<=c;
end process;
end Behavioral;

The above code has been executed and has been found to have no errors..!  plz do comment..!
thank u..!! :) :)  

--vhdl code for leading one's in structural style:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity leading1 is
port(a:in std_logic_vector(4 downto 0);
count:out integer);
end leading1;

architecture Behavioral of leading1 is
signal b,c,d,x:integer;
begin
with a select
count<=x+1 when "11111",
       x when others;
with a(4 downto 1) select
  x<=b+1 when "1111",
      b when others;
with a(4 downto 2) select  
b<= c+1 when "111",
   c when others;
with a(4 downto 3) select  
   c<= d+1 when "11",
    d when others;
with a(4) select
d <= 1 when '1',
    0 when others;
 
end Behavioral;


The above code has been executed and has been found to have no errors..!  plz do comment..!thank u..!! :) :)

vhdl code for leading 1's in dataflow style

library ieee;

entity leading1s is
port(a:in bit_vector(3 downto 0);
y:out bit_vector(2 downto 0));
end leading1s;

architecture arch of leading1s is
begin
y(2)<=(a(3) and a(2) and a(1) and a(0));
y(1)<=(a(3) and a(2) and (a(1) xor a(0)));
y(0)<=((a(3) and (not a(2))) or (a(3) and (not a(0)) and  a(1)));
end arch; 

The above code has been executed and has been found to 

have no errors..!  plz do comment..!
thank u..!! :) :)  

--3 bit comparator using subtractor:

--code for full subtractor:





entity bit3_comp_subt is
port(a,b:in bit_vector(2 downto 0);
bin:in bit;
aeb,agb,alb:out bit);
end bit3_comp_subt;

architecture Behavioral of bit3_comp_subt is
component fullsubtractor is
port(a,b,bin:in bit;
d,bout:out bit);
end component;
signal e:bit_vector(1 downto 0);
signal m,n,o,p,bout:bit;
signal d: bit_vector(2 downto 0);
begin 
s1: fullsubtractor port map(a(0),b(0),bin,d(0),e(0));
s2: fullsubtractor port map(a(1),b(1),e(0),d(1),e(1));
s3: fullsubtractor port map(a(2),b(2),e(1),d(2),bout);
aeb<= m;
m<=not (d(0) or d(1) or d(2));
agb<= m nor bout;
alb<=bout;
end Behavioral;


The above code has been executed and has been found to have no errors..!  plz do comment..!

thank u..!! :) :) 

--vhdl code for counter using jk flip flop as component:

--code for jk flip flop (component):


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity jkffl is
port(j,k,rst,clk:in std_logic;
q,qbar:out std_logic);
end jkffl;

architecture Behavioral of jkffl is
begin
process(clk,j,k,rst)
variable x:std_logic:='0';
begin
if (clk' event and clk='1') then
 case rst is
            when '1'=> x:='0';
when '0'=> if (j='0' and k='0')then
          x:=x;
 elsif(j='0' and k='1') then
 x:='0';
 elsif (j='1' and k='0') then
 x:='1';
 elsif(j='1' and k='1')then
 x:=not x;
 end if;
when others=> null;
end case;
end if;
q<= x;
qbar<= not x;
end process;
end Behavioral;



--main code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity jkcounter is
port(clk,rst:in std_logic;
q,qb:inout std_logic_vector(3 downto 0));
end jkcounter;

architecture arch of jkcounter is
component jkffl is
port(j,k,rst,clk:in std_logic;
q,qbar:out std_logic);
end component;
signal k,l,m:std_logic;
begin
k<=q(0);
l<=q(0) and q(1);
m<=q(0) and q(1) and q(2);
a1:jkffl port map('1','1',rst,clk,q(0),qb(0));
a2:jkffl port map(k,k,rst,clk,q(1),qb(1));
a3:jkffl port map(l,l,rst,clk,q(2),qb(2));
a4:jkffl port map(m,m,rst,clk,q(3),qb(3));
end arch;

--for up counter consider the output at q
--for down counter consider the output at qb.

The above code has been executed and has been found to have no errors..!  plz do comment..!

thank u..!! :) : )

111 to 444 counter using binary incrementation method

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(clk: in std_logic;
c1,c2,c3:out std_logic_vector(3 downto 0));
end counter;
architecture arch of counter is
begin
process(clk)
variable t1:std_logic_vector(3 downto 0) :="0001";
variable t2:std_logic_vector(3 downto 0) :="0001";
variable t3:std_logic_vector(3 downto 0) :="0001";
begin
if(clk' event and ck='1')then
t1:=t1+'1';
if(t1="1010")then
t2:=t2+'1';
t1:="0000";
if(t2="1010")then
t3:=t3+'1';
t2:="0000";
end if;
end if;
if(t3="0100" and t2="0100" and t1="0101")then
t1:="0001";
t2:="0001";
t3:="0001";
end if;
end if;
c1<=t1;
c2<=t2;
c3<=t3;
end process;
end arch;

Above code is verified.
Plz do comment! :)
thank you..!

--vhdl code for 16 to 1 mux using for generate.

--code for component : 4 to 1 mux. 


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux_4 is
port(d:in std_logic_vector(3 downto 0);
 e:in std_logic;
 s:in std_logic_vector(1 downto 0);
 y: out std_logic);
end mux_4;
architecture Behavioral of mux_4 is
signal m:std_logic;
begin
with e select
 y<= m when '1',
    '0' when others;
with s select
m<= d(0) when "00",
    d(1) when "01",
d(2) when "10",
d(3) when "11",
'0' when others;
end Behavioral;


--main code..


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity genmux is
port(d:in std_logic_vector(15 downto 0);
s:in std_logic_vector(3 downto 0);
y:out std_logic);
end genmux;
architecture behavioural of genmux is
component mux_4 is
port(d:in std_logic_vector(3 downto 0);
s:in std_logic_vector(1 downto 0);
y:out std_logic);
end component; 
signal x:std_logic_vector(3 downto 0);
begin 
a2:for i in 0 to 3 generate
ai:mux_4 port map(d((((i+1)*4)-1) downto (i*4)),s(1 downto 0),x(i));
end generate;
a5:mux_4 port map(x(3 downto 0),s(3 downto 2),y);
end behavioural;

The above code has been executed and has been found to have no errors..!  plz do comment..!
thank u..!! :) :)