--vhdl code for 4 bit synchronous counter using S R flipflop:
code for S R flip flop:
--here the condition when both S and R inputs are '1' is omitted , because the output for this input combination is undefined.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity srffl is
port(s,r,rst,clk:in std_logic;
q,qb:out std_logic);
end srffl;
architecture Behavioral of srffl is
begin
process
variable x:std_logic:='0';
variable y:std_logic_vector(1 downto 0);
begin
y:=s&r;
wait on clk ;
if (clk' event and clk='1') then
if rst='1' then
x:='0';
elsif y="01" then
x:='0';
elsif y="10" then
x:='1';
elsif y="00" then
x:=x;
end if;
end if;
q<=x;
qb<=not x;
end process;
end Behavioral;
code for counter:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity srcounter is
port(clk,rst:in std_logic;
q,qbar:inout std_logic_vector(3 downto 0));
end srcounter;
architecture Behavioral of srcounter is
component srffl is
port(s,r,rst,clk:in std_logic;
q,qb:out std_logic);
end component;
signal l,m,n,o,p,j:std_logic;
begin
l<=not q(1) and q(0);
m<=q(0) and q(1);
n<=not q(2) and q(1) and q(0);
o<=q(0) and q(1) and q(2);
p<=not q(3) and q(2) and q(1) and q(0);
j<=q(0) and q(1) and q(2) and q(3);
a1:srffl port map(not q(0), q(0),rst,clk,q(0),qbar(0));
a2:srffl port map(l,m,rst,clk,q(1),qbar(1));
a3:srffl port map(n,o,rst,clk,q(2),qbar(2));
a4:srffl port map(p,j,rst,clk,q(3),qbar(3));
end Behavioral;
The above code has been executed and has been found to have no errors..!
plz do comment..!
thank u..!! :) :)
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