--vhdl code for 4 bit counter using d flip flop :
--code for d flip flop:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dffl is
port(d,rst,clk:in std_logic;
q,qb:out std_logic);
end dffl;
architecture Behavioral of dffl is
begin
process
variable x:std_logic:='0';
begin
wait on clk ;
if (clk' event and clk='1') then
if rst='1' then
x:='0';
else
x:=d;
end if;
end if;
q<=x;
qb<=not x;
end process;
end Behavioral;
--code for counter:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dcounter is
port(clk,rst:in std_logic;
q,qbar:inout std_logic_vector(3 downto 0));
end dcounter;
architecture Behavioral of dcounter is
component dffl is
port(d,rst,clk:in std_logic;
q,qb:out std_logic);
end component;
signal i,k,l,m:std_logic;
begin
i<=not q(0);
k<=q(0) xor q(1);
l<=(q(2)and(not q(1) or not q(0))) or ((not q(2)) and q(1) and q(0));
m<=(q(3)and(not q(2) or not q(1) or not q(0))) or ((not q(3)) and q(2) and q(1) and q(0));
a1:dffl port map(i,rst,clk,q(0),qbar(0));
a2:dffl port map(k,rst,clk,q(1),qbar(1));
a3:dffl port map(l,rst,clk,q(2),qbar(2));
a4:dffl port map(m,rst,clk,q(3),qbar(3));
end Behavioral;
The above code has been executed and has been found to have no errors..!
plz do comment..!
thank u..!! :) :)
--code for d flip flop:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dffl is
port(d,rst,clk:in std_logic;
q,qb:out std_logic);
end dffl;
architecture Behavioral of dffl is
begin
process
variable x:std_logic:='0';
begin
wait on clk ;
if (clk' event and clk='1') then
if rst='1' then
x:='0';
else
x:=d;
end if;
end if;
q<=x;
qb<=not x;
end process;
end Behavioral;
--code for counter:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dcounter is
port(clk,rst:in std_logic;
q,qbar:inout std_logic_vector(3 downto 0));
end dcounter;
architecture Behavioral of dcounter is
component dffl is
port(d,rst,clk:in std_logic;
q,qb:out std_logic);
end component;
signal i,k,l,m:std_logic;
begin
i<=not q(0);
k<=q(0) xor q(1);
l<=(q(2)and(not q(1) or not q(0))) or ((not q(2)) and q(1) and q(0));
m<=(q(3)and(not q(2) or not q(1) or not q(0))) or ((not q(3)) and q(2) and q(1) and q(0));
a1:dffl port map(i,rst,clk,q(0),qbar(0));
a2:dffl port map(k,rst,clk,q(1),qbar(1));
a3:dffl port map(l,rst,clk,q(2),qbar(2));
a4:dffl port map(m,rst,clk,q(3),qbar(3));
end Behavioral;
The above code has been executed and has been found to have no errors..!
plz do comment..!
thank u..!! :) :)
4 comments:
Thank you. Seems legit but I haven't run it myself. If you could provide the circuit diagram combining the various D-FF using the signals i, k, l and m it would be better
it is not working on fpga
Ab main kya bolu
Didn't work
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