TechNiPr0

--vhdl code for signed/unsigned/adder/subtractor:

--below given vhdl code is used to add ,subtract signed and unsigned numbers
--here select line named sel is used to perform following operations
 
--sel       operation
--00       add unsigned
--01       add signed
--10       sub unsigned
--11       sub signed


--components  for signed_unsigned_add/sub


--component for signed addition.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.STD_LOGIC_arith.ALL;
entity signed_add is
port(a,b: in std_logic_vector(7 downto 0);
      sum: out std_logic_vector(8 downto 0));
end signed_add;

architecture Behavioral of signed_add is
signal d:std_logic;
signal c,s,p: std_logic_vector(8 downto 0);
begin
d<=a(7) xor b(7);
c(0)<='0';
a1: for i in 0 to 7 generate
 s(i)<=a(i) xor b(i) xor c(i);
 c(i+1)<=(a(i) and b(i)) or (b(i) and c(i))or (c(i)and a(i));
 end generate;
 s(8)<=c(8);
 sum<=p when d='1' else
      s;
p<=not(c(8))&s(7 downto 0);
end Behavioral;


--component for signed subtraction
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity signedsub is
port(a,b: in std_logic_vector(7 downto 0);
      diff: out std_logic_vector(8 downto 0));
end signedsub;

architecture Behavioral of signedsub is
signal d:std_logic;
signal g,h:std_logic_vector(7 downto 0);
signal c,s,p,r: std_logic_vector(8 downto 0);
begin 
g<=not b;
r(0)<='1';
a2:for i in 0 to 7 generate
h(i)<=g(i) xor r(i);
r(i+1)<=g(i) and r(i);
end generate;
d<=a(7) and b(7);
c(0)<='0';
a1: for i in 0 to 7 generate
 s(i)<=a(i) xor h(i) xor c(i);
 c(i+1)<=(a(i) and h(i)) or (h(i) and c(i))or (c(i)and a(i));
 end generate;
 s(8)<=c(8);
 diff<=s when d='0' else
       p;
p<=not(c(8))&s(7 downto 0);
end Behavioral;


--component for unsigned addition

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity unsigned_add is
port(a,b: in std_logic_vector(7 downto 0);
      sum: out std_logic_vector(8 downto 0));
end unsigned_add;

architecture Behavioral of unsigned_add is
signal c: std_logic_vector(8 downto 0);
begin
c(0)<='0';
a1: for i in 0 to 7 generate
 sum(i)<=a(i) xor b(i) xor c(i);
 c(i+1)<=(a(i) and b(i)) or (b(i) and c(i))or (c(i)and a(i));
 end generate;
 sum(8)<=c(8);
end Behavioral;


--component for unsigned subtraction

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity unsigned_sub is
port(a,b: in std_logic_vector(7 downto 0);
      diff: out std_logic_vector(8 downto 0));
end unsigned_sub;

architecture dataflow of unsigned_sub is
signal g,h:std_logic_vector(7 downto 0);
signal c,d,e,r,s: std_logic_vector(8 downto 0);
begin 
g<=not b;
r(0)<='1';
a1:for i in 0 to 7 generate
h(i)<=g(i) xor r(i);
r(i+1)<=g(i) and r(i);
end generate;
c(0)<='0';
a2: for i in 0 to 7 generate
 d(i)<=a(i) xor h(i) xor c(i);
 c(i+1)<=(a(i) and h(i)) or (h(i) and c(i))or (c(i)and a(i));
 end generate;
 d(8)<='0';
 diff<=d when c(8)='1' else
       e;
s(0)<='1';
a3:for i in 0 to 7 generate
e(i)<=(not d(i)) xor s(i);
s(i+1)<=(not d(i)) and s(i);
end generate;
e(8)<='0';
end dataflow;



--main code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sig_unsig_add_sub is
port(a,b:in std_logic_vector(7 downto 0);
sel:in std_logic_vector(1 downto 0);
y:out std_logic_vector(8 downto 0));
end sig_unsig_add_sub;

architecture Behavioral of sig_unsig_add_sub is
component signed_add is
port(a,b: in std_logic_vector(7 downto 0);
      sum: out std_logic_vector(8 downto 0));
end component;
component signedsub is
port(a,b: in std_logic_vector(7 downto 0);
      diff: out std_logic_vector(8 downto 0));
end component;
component unsigned_add is
port(a,b: in std_logic_vector(7 downto 0);
      sum: out std_logic_vector(8 downto 0));
end component;
component unsigned_sub is
port(a,b: in std_logic_vector(7 downto 0);
      diff: out std_logic_vector(8 downto 0));
end component;
signal m,n,o,p:std_logic_vector(8 downto 0);
begin
n1:signed_add port map(a,b,m);
n2:signedsub port map(a,b,n);
n3:unsigned_add port map(a,b,o);
n4:unsigned_sub port map(a,b,p);

y<=m when sel="01" else
   n when sel="11" else
o when sel="00" else
p;
end Behavioral; 


The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :