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--vhdl code for signed multiplier using functions:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity signedmultiplier is
generic(n:integer:=4);
port (a,b :in std_logic_vector(n downto 0);
sgm:out std_logic_vector((n*n) downto 0));
end signedmultiplier;

architecture Behavioral of signedmultiplier is
function conv(m:std_logic_vector)
return integer is
variable x:integer;
begin 
x:=0;
for i in 0 to n loop
if(m(i)='1') then
x:=x+(2**i);
end if;
end loop;
if(m(3)='1')then
x:=(2**4)-x;
end if;
return x;
end conv;
function reconv(j:integer)
return std_logic_vector is
variable y:std_logic_vector((n*n) downto 0):=(others=>'0');
variable l:integer:=0;
begin
l:=j;
while (l>0) loop
for i in ((n*n)-1) downto 0 loop
if(l>=2**i) then
y(i):='1';
l:=l-2**i;
exit;
end if;
end loop;
end loop;
return y;
end reconv;

begin
process(a,b)
variable u,v,t,z,s:integer:=0;
variable c:std_logic:='0';
variable w:std_logic_vector((n*n) downto 0):=(others=>'0');
begin
u:=conv(a);
v:=conv(b);
z:=u*v;
w:=reconv(z);
c:=a(n) xor b(n);
--t:=z;
if(c='1') then
w(n*n):='1';
s:=2**(n*n);
for i in ((n*n)-1) downto 0 loop
t:=s-(2**i);
if(t>=z) then
s:=t;
w(i):='1';
else
w(i):='0';
end if;
end loop;
end if;
sgm<=w;
end process;
end Behavioral;



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
entity datatransmitter is
port(data:in std_logic_vector(6 downto 0);
clk,data_ready:in std_logic;
dout:out std_logic);
end datatransmitter;

architecture Behavioral of datatransmitter is
begin
process(clk,data_ready)
variable x:std_logic_vector(9 downto 0);
variable y:std_logic;
begin
y:=data(0)xor data(1)xor data(2)xor data(3)xor data(4)xor data(5)xor data(6);
if(data_ready='0') then
dout<='0';
x:='1'&data&y&'1';
elsif(clk' event and clk='1') then
dout<=x(9);
x:=x(8 downto 0)&'0';
end if;
end process;
end Behavioral;



The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)

--vhdl code for signed/unsigned/adder/subtractor:

--below given vhdl code is used to add ,subtract signed and unsigned numbers
--here select line named sel is used to perform following operations
 
--sel       operation
--00       add unsigned
--01       add signed
--10       sub unsigned
--11       sub signed


--components  for signed_unsigned_add/sub


--component for signed addition.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.STD_LOGIC_arith.ALL;
entity signed_add is
port(a,b: in std_logic_vector(7 downto 0);
      sum: out std_logic_vector(8 downto 0));
end signed_add;

architecture Behavioral of signed_add is
signal d:std_logic;
signal c,s,p: std_logic_vector(8 downto 0);
begin
d<=a(7) xor b(7);
c(0)<='0';
a1: for i in 0 to 7 generate
 s(i)<=a(i) xor b(i) xor c(i);
 c(i+1)<=(a(i) and b(i)) or (b(i) and c(i))or (c(i)and a(i));
 end generate;
 s(8)<=c(8);
 sum<=p when d='1' else
      s;
p<=not(c(8))&s(7 downto 0);
end Behavioral;


--component for signed subtraction
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity signedsub is
port(a,b: in std_logic_vector(7 downto 0);
      diff: out std_logic_vector(8 downto 0));
end signedsub;

architecture Behavioral of signedsub is
signal d:std_logic;
signal g,h:std_logic_vector(7 downto 0);
signal c,s,p,r: std_logic_vector(8 downto 0);
begin 
g<=not b;
r(0)<='1';
a2:for i in 0 to 7 generate
h(i)<=g(i) xor r(i);
r(i+1)<=g(i) and r(i);
end generate;
d<=a(7) and b(7);
c(0)<='0';
a1: for i in 0 to 7 generate
 s(i)<=a(i) xor h(i) xor c(i);
 c(i+1)<=(a(i) and h(i)) or (h(i) and c(i))or (c(i)and a(i));
 end generate;
 s(8)<=c(8);
 diff<=s when d='0' else
       p;
p<=not(c(8))&s(7 downto 0);
end Behavioral;


--component for unsigned addition

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity unsigned_add is
port(a,b: in std_logic_vector(7 downto 0);
      sum: out std_logic_vector(8 downto 0));
end unsigned_add;

architecture Behavioral of unsigned_add is
signal c: std_logic_vector(8 downto 0);
begin
c(0)<='0';
a1: for i in 0 to 7 generate
 sum(i)<=a(i) xor b(i) xor c(i);
 c(i+1)<=(a(i) and b(i)) or (b(i) and c(i))or (c(i)and a(i));
 end generate;
 sum(8)<=c(8);
end Behavioral;


--component for unsigned subtraction

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity unsigned_sub is
port(a,b: in std_logic_vector(7 downto 0);
      diff: out std_logic_vector(8 downto 0));
end unsigned_sub;

architecture dataflow of unsigned_sub is
signal g,h:std_logic_vector(7 downto 0);
signal c,d,e,r,s: std_logic_vector(8 downto 0);
begin 
g<=not b;
r(0)<='1';
a1:for i in 0 to 7 generate
h(i)<=g(i) xor r(i);
r(i+1)<=g(i) and r(i);
end generate;
c(0)<='0';
a2: for i in 0 to 7 generate
 d(i)<=a(i) xor h(i) xor c(i);
 c(i+1)<=(a(i) and h(i)) or (h(i) and c(i))or (c(i)and a(i));
 end generate;
 d(8)<='0';
 diff<=d when c(8)='1' else
       e;
s(0)<='1';
a3:for i in 0 to 7 generate
e(i)<=(not d(i)) xor s(i);
s(i+1)<=(not d(i)) and s(i);
end generate;
e(8)<='0';
end dataflow;



--main code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sig_unsig_add_sub is
port(a,b:in std_logic_vector(7 downto 0);
sel:in std_logic_vector(1 downto 0);
y:out std_logic_vector(8 downto 0));
end sig_unsig_add_sub;

architecture Behavioral of sig_unsig_add_sub is
component signed_add is
port(a,b: in std_logic_vector(7 downto 0);
      sum: out std_logic_vector(8 downto 0));
end component;
component signedsub is
port(a,b: in std_logic_vector(7 downto 0);
      diff: out std_logic_vector(8 downto 0));
end component;
component unsigned_add is
port(a,b: in std_logic_vector(7 downto 0);
      sum: out std_logic_vector(8 downto 0));
end component;
component unsigned_sub is
port(a,b: in std_logic_vector(7 downto 0);
      diff: out std_logic_vector(8 downto 0));
end component;
signal m,n,o,p:std_logic_vector(8 downto 0);
begin
n1:signed_add port map(a,b,m);
n2:signedsub port map(a,b,n);
n3:unsigned_add port map(a,b,o);
n4:unsigned_sub port map(a,b,p);

y<=m when sel="01" else
   n when sel="11" else
o when sel="00" else
p;
end Behavioral; 


The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :

--vhdl code for 4 bit counter using d flip flop :

--code for d flip flop:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dffl is
port(d,rst,clk:in std_logic;
q,qb:out std_logic);
end dffl;

architecture Behavioral of dffl is
begin
process
variable x:std_logic:='0';
begin
wait on clk ;
if (clk' event and clk='1') then
if rst='1' then
x:='0';
else
x:=d;
end if;
end if;
q<=x;
qb<=not x;
end process;
end Behavioral;

--code for counter:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dcounter is
port(clk,rst:in std_logic;
q,qbar:inout std_logic_vector(3 downto 0));
end dcounter;

architecture Behavioral of dcounter is
component dffl is
port(d,rst,clk:in std_logic;
q,qb:out std_logic);
end component;
signal i,k,l,m:std_logic;
begin
i<=not q(0);
k<=q(0) xor q(1);
l<=(q(2)and(not q(1) or not q(0))) or ((not q(2)) and q(1) and q(0));
m<=(q(3)and(not q(2) or not q(1) or not q(0))) or ((not q(3)) and q(2) and q(1) and q(0));
a1:dffl port map(i,rst,clk,q(0),qbar(0));
a2:dffl port map(k,rst,clk,q(1),qbar(1));
a3:dffl port map(l,rst,clk,q(2),qbar(2));
a4:dffl port map(m,rst,clk,q(3),qbar(3));
end Behavioral;

The above code has been executed and has been found to have no errors..!  
plz do comment..!
thank u..!! :) :)

--vhdl code for 4 bit synchronous counter using S R flipflop:

code for S R flip flop:

--here the condition when both S and R inputs are '1' is omitted , because the output for this input combination is undefined.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity srffl is
port(s,r,rst,clk:in std_logic;
q,qb:out std_logic);
end srffl;

architecture Behavioral of srffl is
begin
process
variable x:std_logic:='0';
variable y:std_logic_vector(1 downto 0);
begin
y:=s&r;
wait on clk ;
if (clk' event and clk='1') then
if rst='1' then
x:='0';
elsif y="01" then
x:='0';
elsif y="10" then
x:='1';
elsif y="00" then
x:=x;
end if;
end if;
q<=x;
qb<=not x;
end process;
end Behavioral;

code for counter:


thank u..!! :) :)